`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:40:01 11/03/2011
// Design Name:   SNESController
// Module Name:   C:/Users/david/Desktop/16bitcpu/SNESController_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: SNESController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module SNESController_test;

	// Inputs
	reg clock;
	reg reset;
	reg data;

	// Outputs
	wire latch;
	wire pulse;
	wire [11:0] plyr_input;

	// Instantiate the Unit Under Test (UUT)
	SNESController uut (
		.clock(clock), 
		.reset(reset), 
		.latch(latch), 
		.pulse(pulse), 
		.data(data), 
		.plyr_input(plyr_input)
	);

	initial begin
		// Initialize Inputs
		clock = 0;
		reset = 0;
		data = 1;

		// Wait 100 ns for global reset to finish
		#100;
		reset =1;
		#100;
		reset=0;
        
		// Add stimulus here

	end
	
	always begin
		#10 clock=~clock;
	end
      
	always begin
		#20 data=~data;
	end
		
endmodule

